1. Field of Invention
The present invention relates to a flash memory cell structure. More particularly, the present invention relates to a flash memory cell structure capable of resisting a high dose of radiation.
2. Description of Related Art
When a flash memory unit operates inside a radioactive environment, photons having energy in excess of 4.3 eV may be transferred to electrons so that the electrons jump an energy barrier and radiate. If the electron is located within an oxide layer, the electron may be rapidly transferred to a substrate or control gate due to the effect of an electric field. In general, electrons lost in this manner may lead to a lowering of threshold voltage for the flash memory cells.
A conventional MNOS type of memory cell provides some radiation resistance. However, the coupling constant of a MNOS memory cell is too low to meet the demands of a flash memory.
In a conventional NROM memory cell structure, size of the drain terminal and the source terminal is almost identical, or else, the drain terminal is bigger than the source terminal. This often leads to source-side injection of the memory cell and problems such as second bit effect, thereby affecting the performance of the NROM.
Thus, although a MNOS memory cell is capable of resisting radiation, a low coupling constant renders it useless as a flash memory cell. Yet, the popular NROM structure has some drawbacks including source-side injection and problems due to second bit effect. Thus, how to produce a radiation resistant NROM flash memory cell is still a major research topic.
Accordingly, one object of the present invention is to provide a hexagonal gate flash memory cell capable of resisting intense radiation but having a reduced source-side injection as well as second bit effect so that the memory cell has a relatively constant threshold voltage despite operating in a radioactive environment.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a radiation resistant hexagonal gate flash memory cell. The flash memory cell includes a substrate, a source region located within the substrate, a drain region also located within the substrate and a gate structure. The gate structure is formed over the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer and a control gate layer sequentially stacked over the substrate. The gate structure has a hexagonal profile when viewed from the top. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer.
This invention also provides a radiation resistant flash memory cell. The flash memory cell includes a substrate, a source region located within the substrate, a drain region also located within the substrate and a gate structure. A channel region is formed between the drain region and the source region. The gate structure is formed over the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer and a control gate structure sequentially stacked over the substrate in a direction perpendicular to the channel region. Width of the gate structure increases from the source region to a pre-determined location. Thereafter, width of the gate structure decreases towards the drain region. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer.
This invention also provides an alternative radiation resistant flash memory cell. The flash memory cell includes a substrate, a source region, a drain region and a gate structure. A channel region is formed between the drain region and the source region. The gate structure is formed over the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer. In a direction perpendicular to the channel region, width of the gate structure increases from the source region to a pre-determined location. Thereafter, width of the gate structure decreases towards the drain region. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer. To program codes into the flash memory cell, the section of the gate structure close to the source region serves as an equivalent source region so that size of the equivalent source region is greater than the drain region, thereby preventing second bit effect.
In the aforementioned memory cell structure, the pre-determined location may lie close to the center of symmetry of the gate structure. In addition, width of the gate structure increases from the source region along a direction perpendicular to the channel up until the pre-determined location. Thereafter, width of the gate structure decreases towards the drain region. Such an expansion and contraction of width along a direction perpendicular to the channel ultimately forms a gate having a roughly hexagonal profile.
This invention also provides a radiation resistant flash memory cell. The flash memory cell includes a substrate, a source region, a drain region and a gate structure. A channel region is formed between the drain region and the source region. The gate structure is formed over the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer. In a direction perpendicular to the channel region, width of the gate structure is greater than both the drain region and the source region. In other words, the gate structure has a wide waist profile. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer. To program codes into the flash memory cell, the section of the gate structure close to the source region serves as an equivalent source region so that size of the equivalent source region is greater than the drain region, thereby preventing second bit effect.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.